A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

2019/03/12 by Wanghua Wu, Chih-Wei Yao, Kunal Godbole +8 · 13 citations
Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Photonic and Optical Devices

paper · doi:10.1109/jssc.2019.2899726

Abstract

An analog fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">2 × 2 </tex-math></inline-formula> multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Citations

• An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power

Cited by

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• A Wideband LO Generator for 5G FR1 Bands Using a Single LC -VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
• A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm
• A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
• An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths
• A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
• A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
• Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop
• A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
• A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator. [europepmc]
• An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [europepmc]

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