Kunal Godbole

1. A 28-nm 75-fs_rms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
   2019/03/12 by Wanghua Wu, Chih-Wei Yao, Kunal Godbole +8 · 13 citations
   Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Photonic and Optical Devices