Chih-Wei Yao

1. A 28-nm 75-fs_rms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
   2019/03/12 by Wanghua Wu, Chih-Wei Yao, Kunal Godbole +8 · 13 citations
   Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Photonic and Optical Devices
2. A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
   2021/09/21 by Wanghua Wu, Chih-Wei Yao, Chengkai Guo +6 · 14 citations
   Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Photonic and Optical Devices