A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

2023/09/18 by Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro +6 · 7 citations
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Semiconductor Lasers and Optical Devices

paper · doi:10.1109/jssc.2023.3311681

Abstract

This work presents a low-spur and low-jitter fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word (FCW) subtractive dithering technique randomizes the quantization error of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">Δ Σ </tex-math></inline-formula> modulator driving the PLL divider ratio without requiring an increased DTC dynamic range and pushing the fractional spurs outside the PLL bandwidth. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.33 mm2 and dissipates 17.2 mW. At fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> channels near 9.25 GHz, the measured in-band fractional spurs and the rms jitter are below −70 dBc and 77 fs, respectively, leading to a jitter-power figure of merit of −249.9 dB.

Citations

• A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
• A Wideband 2.4-GHz Delta-Sigma Fractional-&gt;tex&lt;N&gt;/tex&lt;PLL With 1-Mb/s In-Loop Modulation
• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
• Power‐jitter trade‐off analysis in digital‐to‐time converters
• A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications
• A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
• A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
• A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

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• A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference
• A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
• A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
• An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths
• A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
• A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
• Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

Related

• A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
• A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
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• A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO