2024/09/25 by Francesco Tesolin, Simone M. Dartizio, Giacomo Castoro +5
Engineering · #Semiconductor Lasers and Optical Devices #Radio Frequency Integrated Circuit Design #Advancements in PLL and VCO Technologies
paper · doi:10.1109/jssc.2024.3460178
This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">μ </tex-math></inline-formula> s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.