A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

2018/12/28 by Zhirui Zong, Peng Chen, Robert Bogdan Staszewski · 2 citations
Engineering · #Radio Frequency Integrated Circuit Design #Advancements in PLL and VCO Technologies #Microwave Engineering and Waveguides

paper · pdf · doi:10.1109/jssc.2018.2883397

Abstract

In this paper, we propose a 60-GHz fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">1/ f³ </tex-math></inline-formula> ) and thermal ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">1/ f² </tex-math></inline-formula> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">Σ Δ </tex-math></inline-formula> dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">1/ f³ </tex-math></inline-formula> PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.

Citations

• An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Cited by

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