A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference

2024/08/30 by Dingxin Xu, Yuncheng Zhang, Hóngyè Huáng +11
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Microwave Engineering and Waveguides

paper · doi:10.1109/jssc.2024.3447021

Abstract

This work presents a 6.5-to-8-GHz cascaded dual-fractional-N digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer-N mode and an integrated jitter of 190.8 fs in fractional-N mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of −242.9 dB. The fractional spur at near-integer channel is as low as −52.79 dBc, and the reference spur is −72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm2 core area.

Citations

• A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
• An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
• A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
• A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
• Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
• A Wideband LO Generator for 5G FR1 Bands Using a Single LC -VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier

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