A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC

2024/12/04 by Pietro Salvi, Simone M. Dartizio, Michele Rossoni +4
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Semiconductor Lasers and Optical Devices

paper · doi:10.1109/jssc.2024.3501196

Abstract

This work presents a digital-to-time converter (DTC)-based fractional-N phase-locked loop (PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse-constant-slope (R-ICS) DTC, the DTC random jitter is drastically reduced while retaining the excellent linearity performance of the conventional ICS-DTC architecture. Moreover, a tailored DTC range reduction technique is introduced to further improve DTC random noise. The PLL prototype has been fabricated in 28-nm CMOS and consumes 16.7 mW, with an active area of 0.21 mm2. It generates an output frequency in the 8.75–10.25-GHz range from a 125-MHz input reference frequency. At 9.25-GHz near-integer channels, it achieves a 67-fs rms jitter, a −108.5-dBc/Hz in-band phase noise (at 10-kHz offset), and fractional spurs below −63 dBc.

Citations

• A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
• Power‐jitter trade‐off analysis in digital‐to‐time converters
• A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications
• A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
• A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
• A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
• A Wideband LO Generator for 5G FR1 Bands Using a Single LC -VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
• A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

Related

• A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
• A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
• A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
• A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO