A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

2024/01/17 by Zonglin Ye, Xinlin Geng, Yao Xiao +2 · 1 citation
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Radio Frequency Integrated Circuit Design

paper · doi:10.1109/jssc.2023.3339679

Abstract

A 24–28-GHz sub-50-fsrms jitter fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> charge pump phase-locked loop (CPPLL) is presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase-frequency detector (TAPFD) structure is proposed to suppress the in-band noise of charge pump (CP) and cancel the quantization error (QE) simultaneously while keeping low power consumption. Moreover, a cascadable DTC gear estimation and nonlinearity compensation algorithm (NLC) is also proposed to mitigate the fractional spur. The presented PLL achieves a measured integrated rms jitter including spurs of 37.1 fs with −255.2-dB FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">_J </tex-math></inline-formula> for integer- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> channel and 45.6 fs with −253.0-dB FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">_J </tex-math></inline-formula> for fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">N </tex-math></inline-formula> channel.

Citations

• An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
• A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
• A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Cited by

• A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC

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