A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC

2024/10/07 by Michele Rossoni, Simone M. Dartizio, Francesco Tesolin +5 · 1 citation
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Semiconductor Lasers and Optical Devices

paper · doi:10.1109/jssc.2024.3469556

Abstract

This article presents a fractional-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> digital-to-time converter (DTC)-based digital phase-locked loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL adopts a novel DTC circuit, denoted as reverse-concavity variable-slope (VS), which breaks the tradeoff between power consumption, phase noise, and linearity, which is typical of conventional VS-DTCs. A dedicated digital algorithm, working in the background of the PLL, is introduced to minimize DTC nonlinearity. The PLL prototype, fabricated in 28-nm bulk CMOS, has an active area of 0.21 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 17.5 mW. At the near-integer channel around 8.75 GHz, it shows a worst case fractional spur of −63.4 dBc and an integrated rms jitter of 57.3 fs, including spurs. This results in a power-jitter figure of merit of −252.4 dB.

Citations

• A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
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• Power‐jitter trade‐off analysis in digital‐to‐time converters
• A Sub-mW Fractional-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;N &lt;/tex-math&gt; &lt;/inline-formula&gt; ADPLL With FOM of −246 dB for IoT Applications
• A 28-nm 75-fs_rms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
• A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-<i>N</i> Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
• A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<i>N</i> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
• A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

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