Power‐jitter trade‐off analysis in digital‐to‐time converters

2017/01/19 by A. Santiccioli, Alessio Santiccioli, Carlo Samori +5 · 7 citations
Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Electromagnetic Compatibility and Noise Suppression

paper · doi:10.1049/el.2016.4577

Abstract

Digital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period.

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