Alessio Santiccioli

1. Power‐jitter trade‐off analysis in digital‐to‐time converters
   2017/01/19 by A. Santiccioli, Alessio Santiccioli, C. Samori +5 · 7 citations
   Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Electromagnetic Compatibility and Noise Suppression
2. A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
   2020/09/03 by Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi +5 · 7 citations
   Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Radio Frequency Integrated Circuit Design