Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

2018/04/16 by Ahmed Elkholy, Saurabh Saxena, Guanghua Shu +2 · 2 citations
Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Radio Frequency Integrated Circuit Design

paper · doi:10.1109/jssc.2018.2817602

Abstract

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz-1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.

Citations

• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
• Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
• A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
• Power‐jitter trade‐off analysis in digital‐to‐time converters

Cited by

• A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
• An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [europepmc]

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