A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm

2024/09/18 by Seheon Jang, Munjae Chae, Hangi Park +2
Engineering · #Advancements in PLL and VCO Technologies #Photonic and Optical Devices #Semiconductor Lasers and Optical Devices

paper · doi:10.1109/jssc.2024.3456105

Abstract

This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon area, the LC voltage-controlled oscillator (VCO) incorporated a compact three-turn inductor. Then, to still achieve low jitter, the bandwidth of the PLL was designed to be wide to suppress the poor phase noise of this VCO. To mitigate in-band noise, a digital-to-time converter (DTC) was employed to cancel the quantization noise (Q-noise) from the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">Δ Σ </tex-math></inline-formula>M, and a phase selector (PSEL) was used to reduce the thermal noise of the DTC. The effectiveness of these jitter-reduction techniques relies on digital background calibration. However, conventional multi-variable calibrators (MVCs), which utilize the least-mean-squares (LMS) algorithm, suffer from a prolonged convergence time. To overcome this limitation, this work introduced a recursive least-squares (RLS)-based MVC using a dichotomous coordinate descent (DCD) algorithm that can facilitate rapid calibration at a moderate implementation cost. The proposed DCD-RLS MVC achieved a calibration time of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">7.2~μ </tex-math></inline-formula>s, which was 40 times faster than the LMS MVC. The DPLL of this work achieved 88 fsrms jitter at a near-integer-N channel with 68-dBc fractional spurs. Fabricated using a 40-nm CMOS process, it occupied only a 0.12-mm2 active area and consumed 15.7 mW of power.

Citations

• An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
• A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-\rm fs_{\rm rms} Integrated Jitter at 4.5-mW Power
• Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers
• A 28-nm 75-fs_rms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
• A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
• A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-<i>N</i> Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
• A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
• A Low-Spur and Low-Jitter Fractional- <i>N</i> Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
• Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
• A Wideband LO Generator for 5G FR1 Bands Using a Single <i>LC</i> -VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier

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