Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015)

2015/08/25 by Frank Hannig, Hannig, Frank, Dirk Koch +3 · 18 citations
Computer Science · #Distributed #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel #Programming Languages (cs.PL) #and Cluster Computing (cs.DC) #cs.AR #cs.DC #cs.PL

paper · pdf · doi:10.48550/arxiv.1508.06320

Website of the workshop: https://www12.cs.fau.de/ws/fsp2015/

arxiv created 2015/08/25 · openalex publication_date 2015/08/25 · arxiv updated 2015/08/27 · openalex created_date 2022/10/03 · openalex updated_date 2026/07/28

Abstract

This volume contains the papers accepted at the Second International Workshop on FPGAs for Software Programmers (FSP 2015), held in London, United Kingdom, September 1st, 2015. FSP 2015 was co-located with the International Conference on Field Programmable Logic and Applications (FPL).

Cited by

• Allowing Software Developers to Debug HLS Hardware
• Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits
• ThreadPoolComposer - An Open-Source FPGA Toolchain for Software Developers
• Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies
• Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC
• Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service
• Designing Hardware/Software Systems for Embedded High-Performance Computing
• RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment
• Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems
• Performance monitoring for multicore embedded computing systems on FPGAs
• Virtualization Architecture for NoC-based Reconfigurable Systems
• Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA
• Transparent hardware synthesis of Java for predictable large-scale distributed systems
• OpenCL 2.0 for FPGAs using OCLAcc
• A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example
• DSL-based Design Space Exploration for Temporal and Spatial Parallelism of Custom Stream Computing
• Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay
• GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs
• RIPL: An Efficient Image Processing DSL for FPGAs

Related

• Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014)
• Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016)
• Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017)
• Proceedings 15th Workshop on Quantitative Aspects of Programming Languages and Systems
• Proceedings of the 16th Workshop in Logic-based Methods in Programming Environments (WLPE2006)