2015/08/27 by Konrad Möller, Möller, Konrad, Martin Kumm +5
Computer Science · Engineering · #Embedded Systems Design Techniques #Real-time simulation and control systems #VLSI and FPGA Design Techniques #cs.AR
paper · pdf · doi:10.48550/arxiv.1508.06811
Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320)
arxiv created 2015/08/27 · arxiv updated 2015/08/28
We present a tool flow and results for a model-based hardware design for FPGAs from Simulink descriptions which nicely integrates into existing environments. While current commercial tools do not exploit some high-level optimizations, we investigate the promising approach of using reusable subcircuits for folding transformations to control embedded multiplier usage and to optimize logic block usage. We show that resource improvements of up to 70% compared to the original model are possible, but it is also shown that subcircuit selection is a critical task. While our tool flow provides good results already, the investigation and optimization of subcircuit selection is clearly identified as an additional keypoint to extend high-level control on low-level FPGA mapping properties.