2015/08/28 by Markus Vogt, Gerald Hempel, Vogt, Markus +6
Computer Science · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Interconnection Networks and Systems #Other Computer Science (cs.OH) #Parallel Computing and Optimization Techniques #cs.OH
paper · pdf · doi:10.48550/arxiv.1509.00025
Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320)
openalex publication_date 2015/08/28 · arxiv created 2015/09/23 · arxiv updated 2015/09/24 · openalex created_date 2016/06/24 · openalex updated_date 2026/07/28
In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.