2015/08/27 by Véstias, Mário P., Duarte, Rui Policarpo, Neto, Horácio C.
#FOS: Computer and information sciences #Hardware Architecture (cs.AR)
paper · doi:10.48550/arxiv.1508.06832
In this work, we propose an architecture and methodology to design hardware/software systems for high-performance embedded computing on FPGA. The hardware side is based on a many-core architecture whose design is generated automatically given a set of architectural parameters. Both the architecture and the methodology were evaluated running dense matrix multiplication and sparse matrix-vector multiplication on a ZYNQ-7020 FPGA platform. The results show that using a system-level design of the system avoids complex hardware design and still provides good performance results.