2015/08/27 by Daniel Jiménez-González, Carlos Álvarez, Jiménez-González, Daniel +11
Computer Science · Engineering · #Distributed #FOS: Computer and information sciences #Low-power high-performance VLSI design #Numerical Methods and Algorithms #Parallel #Parallel Computing and Optimization Techniques #Performance (cs.PF) #and Cluster Computing (cs.DC) #cs.DC #cs.PF
paper · pdf · doi:10.48550/arxiv.1508.06830
Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320)
arxiv created 2015/08/27 · openalex publication_date 2015/08/27 · arxiv updated 2015/08/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Heterogeneous computing is emerging as a mandatory requirement for power-efficient system design. With this aim, modern heterogeneous platforms like Zynq All-Programmable SoC, that integrates ARM-based SMP and programmable logic, have been designed. However, those platforms introduce large design cycles consisting on hardware/software partitioning, decisions on granularity and number of hardware accelerators, hardware/software integration, bitstream generation, etc. This paper presents a performance parallel heterogeneous estimation for systems where hardware/software co-design and run-time heterogeneous task scheduling are key. The results show that the programmer can quickly decide, based only on her/his OmpSs (OpenMP + extensions) application, which is the co-design that achieves nearly optimal heterogeneous parallel performance, based on the methodology presented and considering only synthesis estimation results. The methodology presented reduces the programmer co-design decision from hours to minutes and shows high potential on hardware/software heterogeneous parallel performance estimation on the Zynq All-Programmable SoC.