A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

2014/02/04 by Masum Hossain, Farrukh Aquil, P.S. Chau +13
Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Low-power high-performance VLSI design

paper · doi:10.1109/jssc.2013.2297403

Abstract

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.

Citations

• A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

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