A fast-lock mixed-mode DLL using a 2-b SAR algorithm

2001/01/01 by Guang-Kaai Dehng, Jyh-Woei Lin, Jyh‐Woei Lin +1
Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Analog and Mixed-Signal Circuit Design

paper · doi:10.1109/4.953474

Abstract

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL, and SARDLL, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The measured RMS and peak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, respectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1 LSB (156 ps).

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