2015/11/03 by Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu +2
Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #CMOS #Computer science #Delay-locked loop #Duty cycle #Electrical engineering #Engineering #Jitter #Optoelectronics #Phase-locked loop #Physics #Power (physics) #Radio Frequency Integrated Circuit Design
paper · doi:10.1109/jssc.2015.2494603
openalex publication_date 2015/11/03 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
In this paper, an all-digital delay-locked loop (ADDLL) with a phase-tracing delay unit (PTDU) has been proposed to achieve wide-operating frequency range, low power, and low cost. For the wide-range DLL, the long delay line is replaced by a PTDU which includes two gated ring oscillators (GROs) for generating the wide delay range with a reduced die area. According to the dual-loop control scheme in this work, the input clock rising edge and falling edge are tracked independently to ensure that the ADDLL output maintains the duty cycle of the input reference. Furthermore, the ADDLL utilizes an open-loop scheme to achieve fast lock time of five clock cycles for all supported input frequencies. The proposed ADDLL has been fabricated in TSMC 90 nm CMOS technology and supports a wide-operating frequency range from 6.7 MHz to 1.24 GHz within a small active area of 0.0318 mm2. The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs, respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz.