A 256-Mb SDRAM using a register-controlled digital DLL

1997/01/01 by A. Hatakeyama, H. Mochizuki, T. Aikawa +24
Engineering · #Advancements in PLL and VCO Technologies #Low-power high-performance VLSI design #Analog and Mixed-Signal Circuit Design

paper · doi:10.1109/4.641693

Abstract

This paper describes the key technologies used in a 256-Mb synchronous DRAM with a clock access time of 1 ns. This DRAM is stable against temperature, voltage, and process variation through the use of a register-controlled digital delay-locked loop (RDLL). The total timing error of the RDLL is about 0.4 ns, sufficient for high frequency operation at 150 to 200 MHz. Unlike most conventional high-density DRAMs, the bit lines are placed above the storage capacitors in this DRAM to relax the design rules of the core area. The noise issues were analyzed and resolved to help implement the technology for mass production of 0.28- to 0.24-/spl mu/m 200-MHz DRAMs.

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