Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

2015/02/14 by Krauss, Tillmann, Wessely, Frank, Schwalke, Udo
#FOS: Physical sciences #Mesoscale and Nanoscale Physics (cond-mat.mes-hall)

paper · doi:10.48550/arxiv.1502.04181

Abstract

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.

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