Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design

2014/05/29 by Tillmann Krauss, Krauss, Tillmann, Frank Wessely +3
Engineering · Physics and Astronomy · #Advancements in Semiconductor Devices and Circuit Design #FOS: Physical sciences #Materials Science (cond-mat.mtrl-sci) #Mesoscale and Nanoscale Physics (cond-mat.mes-hall) #Nanowire Synthesis and Applications #Semiconductor materials and devices #cond-mat.mes-hall #cond-mat.mtrl-sci

paper · pdf · doi:10.48550/arxiv.1405.7562

6 pages, 14 figures, rejected paper ESSDERC 2014

arxiv created 2014/05/29 · openalex publication_date 2014/05/29 · arxiv updated 2014/05/30 · openalex created_date 2022/10/01 · openalex updated_date 2026/07/28

Abstract

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying a control-gate voltage, which significantly increases the flexibility and versatility in digital integrated circuits.

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