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Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education

2025/09/24 by Ian McDougall, Harish Batchu, McDougall, Ian +5
Computer Science · Engineering · #Embedded Systems Design Techniques #Experimental Learning in Engineering #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #VLSI and Analog Circuit Testing

paper · pdf · doi:10.48550/arxiv.2509.20514

openalex publication_date 2025/09/24 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish three goals in relation to this outlook. First, we propose a set of criteria for evaluating the components of a RISC-V implementation's ecosystem from a pedagogical perspective. Second, we analyze a number of existing open-source RISC-V implementations to determine how many of the criteria they fulfill. We then develop a comprehensive solution that meets all of these criterion and is released open-source for other instructors to use. The framework is developed in a composable way that it's different components can be disaggregated per individual course needs. Finally, we also report on a limited study of student feedback.

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