2023/04/06 by Marwan Shaban, Shaban, Marwan, Adam J. Rocke +1
Computer Science · #Architecture #Assembly language #Code (set theory) #Computer architecture #Computer architecture simulator #Computer science #Distributed and Parallel Computing Systems #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Instruction set #Parallel Computing and Optimization Techniques #Parallel computing #Programming language #Reduced instruction set computing #Set (abstract data type) #Software
paper · pdf · doi:10.48550/arxiv.2304.12309
openalex publication_date 2023/04/06 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Simulators for the RISC-V instruction set architecture (ISA) are useful for teaching assembly language and modern CPU architecture concepts. The Assembly/Simulation Platform for Illustration of RISC-V in Education (ASPIRE) is an integrated RISC-V assembler and simulator used to illustrate these concepts and evaluate algorithms to generate machine language code. In this article, ASPIRE is introduced, selected features of the simulator that interactively explain the RISC-V ISA as teaching aides are presented, then two assembly algorithms are evaluated. Both assembly algorithms run in real time as code is being edited in the simulator. The optimized algorithm performs incremental assembly limited to only the portion of the program that is changed. Both algorithms are then evaluated based on overall run-time performance.