WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

2025/03/30 by Giorgi, Roberto, Mariotti, Gianfranco
#FOS: Computer and information sciences #Hardware Architecture (cs.AR)

paper · doi:10.48550/arxiv.2504.03722

Abstract

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline.

Related

• Web-Based Simulator of Superscalar RISC-V Processors
• BRISC-V Emulator: A Standalone, Installation-Free, Browser-Based Teaching Tool
• Optimized Real-Time Assembly in a RISC Simulator
• FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
• CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses