Organization of the Motorola 88110 superscalar RISC microprocessor

1992/04/01 by K. Diefendorff, Markus Allén · 3 citations
Computer Science · #Parallel Computing and Optimization Techniques #Embedded Systems Design Techniques #Advanced Data Storage Technologies #Computer science #Microprocessor #Reduced instruction set computing #Instruction set #Workstation #Operating system #Very long instruction word #Computer architecture #Graphics #Instructions per cycle #Embedded system #Central processing unit #Computer hardware

paper · doi:10.1109/40.127582

openalex publication_date 1992/04/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described.>

Citations

• Dynamic instruction scheduling and the Astronautics ZS-1
• The 801 minicomputer
• Validity of the single processor approach to achieving large scale computing capabilities

Cited by

• The MC88110 implementation of precise exceptions in a superscalar architecture
• The microarchitecture of superscalar processors
• Out-of-order execution [wikipedia]