1993/03/01 by Nasr Ullah, Matt Holle · 1 citation
Computer Science · #Parallel Computing and Optimization Techniques #Embedded Systems Design Techniques #Interconnection Networks and Systems #Computer science #Superscalar #Interrupt #Latency (audio) #Parallel computing #Microprocessor #Out-of-order execution #Microarchitecture #Operating system #Embedded system
paper · doi:10.1145/152479.152482
openalex publication_date 1993/03/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/11
This paper describes the precise exception model of the MC88110 symmetric superscalar microprocessor. The MC88110 is a superscalar, pipelined processor that contains multiple exection units and allows out-of order execution of instructions. The MC88110 implements fully precise exceptions and presents the architecturally correct state to an exception handling routine in a manner that minimizes exception response latency. The interrupt latency timings in the MC88110 are described, and several examples of short and long latencies are provided.