1995/01/01 by James E. Smith, Gurindar S. Sohi · 1 citation
Computer Science · #Parallel Computing and Optimization Techniques #Distributed and Parallel Computing Systems #Embedded Systems Design Techniques #Superscalar #Computer science #Parallel computing #Microarchitecture #Instruction-level parallelism #Speculative execution #Process (computing) #Out-of-order execution #Instructions per cycle #Pipeline burst cache #Parallelism (grammar) #Computer architecture #Computer hardware #Operating system #CPU cache #Cache
paper · doi:10.1109/5.476078
openalex publication_date 1995/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/17
Superscalar processing is the latest in along series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of superscalar processors. We begin with a discussion of the general problem solved by superscalar processors: converting an ostensibly sequential program into a more parallel one. The principles underlying this process, and the constraints that must be met, are discussed. The paper then provides a description of the specific implementation techniques used in the important phases of superscalar processing. The major phases include: (1) instruction fetching and conditional branch processing, (2) the determination of data dependences involving register values, (3) the initiation, or issuing, of instructions for parallel execution, (4) the communication of data values through memory via loads and stores, and (5) committing the process state in correct order so that precise interrupts can be supported. Examples of recent superscalar microprocessors, the MIPS R10000, the DEC 21164, and the AMD K5 are used to illustrate a variety of superscalar methods.