Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors

2012/03/21 by Enrico Prati, Marco De Michielis, Matteo Belli +26 · 2 citations
Engineering · Physics and Astronomy · #Advancements in Semiconductor Devices and Circuit Design #Quantum and electron transport phenomena #Semiconductor materials and devices #cond-mat.mes-hall

paper · pdf · doi:10.1088/0957-4484/23/21/215204

4 Figures

arxiv created 2012/03/21 · openalex publication_date 2012/05/03 · arxiv updated 2015/06/04 · openalex created_date 2020/11/23 · openalex updated_date 2026/07/30

Abstract

We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm² is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices.

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