2002/03/01 by H.‐S. Philip Wong, H.-S. P. Wong · 570 citations
Engineering · Materials Science · #Advancements in Semiconductor Devices and Circuit Design #CMOS #Carbon Nanotubes in Composites #Context (archaeology) #Dielectric #Electrical engineering #Electronic engineering #Engineering #Engineering physics #Field-effect transistor #Gate dielectric #Gate oxide #MOSFET #Materials science #Metal gate #Microelectronics #Nanotechnology #Optoelectronics #Semiconductor materials and devices #Silicon #Transistor #Voltage
paper · doi:10.1147/rd.462.0133
published in IBM Journal of Research and Development 46(2.3), 133-168 (IBM)
crossref issued 2002/03/01 · crossref published 2002/03/01 · crossref published-print 2002/03/01 · openalex publication_date 2002/03/01 · crossref created 2010/04/05 · openalex created_date 2025/10/10 · crossref deposited 2025/10/23 · crossref indexed 2026/08/01 · openalex updated_date 2026/08/01
This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.