1999/05/01 by D. A. Buchanan · 364 citations
Engineering · #Advancements in Semiconductor Devices and Circuit Design #CMOS #Dielectric #Electrical engineering #Electronic engineering #Engineering #Engineering physics #Gate dielectric #Gate oxide #Integrated Circuits and Semiconductor Failure Analysis #Materials science #Optoelectronics #Physics #Process engineering #Process integration #Reliability (semiconductor) #Scaling #Semiconductor materials and devices #Transistor #Voltage
paper · doi:10.1147/rd.433.0245
published in IBM Journal of Research and Development 43(3), 245-264 (IBM)
crossref issued 1999/05/01 · crossref published 1999/05/01 · crossref published-print 1999/05/01 · openalex publication_date 1999/05/01 · crossref created 2010/04/05 · openalex created_date 2025/10/10 · crossref deposited 2025/10/20 · crossref indexed 2026/07/29 · openalex updated_date 2026/07/29
In this paper a review of the more “fundamental” concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.