2025/04/03 by Shengyu Bao, Zongwei Wang, Yuhang Yang +5 · 7 citations
Engineering · Mathematics · #Advanced Memory and Neural Computing #Computer science #Electrical engineering #Electronic engineering #Engineering #Ferroelectric and Negative Capacitance Devices #Isolation (microbiology) #Logic gate #Materials science #Mathematics #NAND gate #Optoelectronics #Resistive random-access memory #Scheme (mathematics) #Semiconductor materials and devices #Voltage
paper · doi:10.1109/ted.2025.3554165
published in IEEE Transactions on Electron Devices 72(5), 2327-2333 (Institute of Electrical and Electronics Engineers)
openalex publication_date 2025/04/03 · openalex created_date 2025/04/04 · openalex updated_date 2026/08/01
In this work, we introduce an innovative NAND-gate array structure that optimizes cell density through local series connection. By implementing a p-well isolation in combination with the substrate bias effect, we effectively mitigate the operating voltage constraints on series-connected cells. This design ensures symmetric read operations and maintains uniform read margins among cells in the NAND-gate array, achieving a record cell size of 0.045 μm2at the 40-nm technology node. This design demonstrates robust reliability with an endurance of 100k cycles and a ten-year retention at 150∘C. Moreover, the implementation of deep trench isolation (DTI) technology enables further density enhancements, with a projected cell area of 0.0255 μm2at the 28-nm technology node. This approach offers significant advancements in resistive random access memory (RRAM) density, making it highly suitable for high-density memory and computing applications.