Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

2015/10/29 by Pai-Yu Chen, Shimeng Yu · 357 citations
Engineering · Materials Science · #Advanced Memory and Neural Computing #Computer science #Electrical engineering #Electronic engineering #Engineering #Ferroelectric and Negative Capacitance Devices #Resistive random-access memory #Resistor #Spice #Transistor #Transition Metal Oxide Nanomaterials

paper · doi:10.1109/ted.2015.2492421

published in IEEE Transactions on Electron Devices 62(12), 4022-4028 (Institute of Electrical and Electronics Engineers)

openalex publication_date 2015/10/29 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

In this paper, we present a compact model for metal-oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed I-V characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model's applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level.

Citations

• Crossbar RRAM Arrays: Selector Device Requirements During Write Operation

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