2015/04/23 by Juhyun Park, Younghwi Yang, Hanwool Jeong +5
Engineering · #Semiconductor materials and devices #Advancements in Semiconductor Devices and Circuit Design #Ferroelectric and Negative Capacitance Devices
paper · doi:10.1109/ted.2015.2420681
A near-threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> region. This paper proposes a read buffer with adjusted the number of fins or V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> to resolve the problems in the near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> region.