A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

2007/04/01 by Shigeki Ohbayashi, S. Ohbayashi, Makoto Yabuuchi +16 · 1 citation
Engineering · #Low-power high-performance VLSI design #Advancements in Semiconductor Devices and Circuit Design #VLSI and FPGA Design Techniques

paper · doi:10.1109/jssc.2007.891648

Abstract

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

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