2022/04/21 by Xinpei Duan, Zhenyu Yang, Jun Lin +8 · 1 citation
Materials Science · Engineering · #2D Materials and Applications #Ferroelectric and Negative Capacitance Devices
paper · doi:10.1109/ted.2022.3164859
Tailoring MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> into nanoribbon (NR) provides an efficient regulation of the electrical property. Herein, high-performance MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors are fabricated by optimizing the channel height, width, and length. The electrical performance of the device is improved due to enhanced gate modulation capability from the quasi-3D channel geometry. The devices obtain a high ON-state current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">496 ~μ A ⋅ μ m </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> while offering appropriate field-effect mobility of 52.6 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> as the height and width of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> NR are fixed to 20 ± 3 nm and 130 ± 10 nm, respectively. The high performance and desirable current saturation are promising to construct robust logic gates. The NOT and NAND gates are assembled based on an individual MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> NR. The inverters demonstrate a voltage gain of −17.8 and a total noise margin of nearly 75%. This work provides an alternative strategy to fully take the advantage of 2-D materials in logic electronics circuits.