2021/10/20 by C. J. Dorow, Chelsey Dorow, Kevin O'Brien +25 · 11 citations
Materials Science · Engineering · #2D Materials and Applications #Nanowire Synthesis and Applications #Advancements in Semiconductor Devices and Circuit Design
paper · doi:10.1109/ted.2021.3118659
2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore’s Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> using novel contact metal show low variation, one of the lowest reported contact resistances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">R_\text c </tex-math></inline-formula> ) of 0.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">kΩ ⋅ μ m </tex-math></inline-formula> , low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> show 89 mV/dec SS, best reported for pMOS on grown films, but ON-current remains behind nMOS. We show <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">R_\text C </tex-math></inline-formula> is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">5× </tex-math></inline-formula> by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are demonstrated as options for wafer-scale TMD channel growth. WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors achieve 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">μ A/μ m </tex-math></inline-formula> ON-current, highest reported on WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an improvement in mobility with proper passivation.