An RC Oscillator With Comparator Offset Cancellation

2016/05/30 by Arun Paidimarri, Danielle Griffith, Alice Wang +2 · 5 citations
Engineering · #Analog and Mixed-Signal Circuit Design #Advancements in PLL and VCO Technologies #Low-power high-performance VLSI design

paper · doi:10.1109/jssc.2016.2559508

Abstract

A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves 4× to 25× temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over -40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to 10× reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.

Cited by

• DustNet: A Wireless Network of Ultrasonic Neural Implants
• A 0.0014 mm 2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the -60 to +40 °C Measurement Range. [europepmc]
• Optoelectronic parametric oscillator. [europepmc]
• An Energy Efficient and Temperature Stable Digital FLL-based Wakeup Timer with Time-Domain Temperature Compensation. [europepmc]
• Methods for Designing High-Precision Relaxation Oscillator. [europepmc]

Related

• Low-power relaxation oscillator with temperature-compensated thyristor decision elements
• CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator
• A 0.03mm² 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing
• Experimental Clock Calibration on a Crystal-Free Mote-on-a-Chip
• A fully-digital semi-rotational frequency detection algorithm for bang-bang CDRs