A 0.03mm² 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing

2024/10/07 by Ray, Yudhajit, Ghosh, Archisman, Sen, Shreyas
#FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · doi:10.48550/arxiv.2410.16310

Abstract

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and accurate clock generation are of the utmost importance. This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system. In this design, the ring oscillator-based PLL can operate a wide frequency range of 100-250MHz while consuming 0.03mm2 of area and 131.8μW of power at 250MHz. The area-normalized figure of merit (FOM) of the integrating SSPLL is found to be -236, while showing a reference spur of -43.2dB.

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