CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

2001/03/01 by D.J. Foley, M.P. Flynn, Michael P. Flynn
Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Electromagnetic Compatibility and Noise Suppression

paper · doi:10.1109/4.910480

Abstract

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0/spl deg/C to 85/spl deg/C. The circuits were fabricated on a generic 0.5-/spl mu/m digital CMOS process.

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