2020/02/12 by Mohammad Saeed Abrishami, Massoud Pedram, Abrishami, Mohammad Saeed +4 · 1 citation
Computer Science · Engineering · #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Machine Learning (cs.LG) #Machine Learning (stat.ML) #Parallel Computing and Optimization Techniques #Signal Processing (eess.SP) #VLSI and FPGA Design Techniques #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2002.05291
openalex publication_date 2020/02/12 · openalex created_date 2020/07/16 · openalex updated_date 2026/07/28
The miniaturization of transistors down to 5nm and beyond, plus the\nincreasing complexity of integrated circuits, significantly aggravate short\nchannel effects, and demand analysis and optimization of more design corners\nand modes. Simulators need to model output variables related to circuit timing,\npower, noise, etc., which exhibit nonlinear behavior. The existing simulation\nand sign-off tools, based on a combination of closed-form expressions and\nlookup tables are either inaccurate or slow, when dealing with circuits with\nmore than billions of transistors. In this work, we present CSM-NN, a scalable\nsimulation framework with optimized neural network structures and processing\nalgorithms. CSM-NN is aimed at optimizing the simulation time by accounting for\nthe latency of the required memory query and computation, given the underlying\nCPU and GPU parallel processing capabilities. Experimental results show that\nCSM-NN reduces the simulation time by up to 6\× compared to a\nstate-of-the-art current source model based simulator running on a CPU. This\nspeedup improves by up to 15\× when running on a GPU. CSM-NN also\nprovides high accuracy levels, with less than 2 % error, compared to HSPICE.\n