2020/02/12 by Mohammad Saeed Abrishami, Hao Ge, Abrishami, Mohammad Saeed +7
Engineering · #Advancements in Semiconductor Devices and Circuit Design #FOS: Computer and information sciences #FOS: Electrical engineering #Low-power high-performance VLSI design #Machine Learning (cs.LG) #Signal Processing (eess.SP) #VLSI and FPGA Design Techniques #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2002.05292
openalex publication_date 2020/02/12 · openalex created_date 2022/07/26 · openalex updated_date 2026/07/28
The shrinking of transistor geometries as well as the increasing complexity\nof integrated circuits, significantly aggravate nonlinear design behavior. This\ndemands accurate and fast circuit simulation to meet the design quality and\ntime-to-market constraints. The existing circuit simulators which utilize\nlookup tables and/or closed-form expressions are either slow or inaccurate in\nanalyzing the nonlinear behavior of designs with billions of transistors. To\naddress these shortcomings, we present NN-PARS, a neural network (NN) based and\nparallelized circuit simulation framework with optimized event-driven\nscheduling of simulation tasks to maximize concurrency, according to the\nunderlying GPU parallel processing capabilities. NN-PARS replaces the required\nmemory queries in traditional techniques with parallelized NN-based computation\ntasks. Experimental results show that compared to a state-of-the-art\ncurrent-based simulation method, NN-PARS reduces the simulation time by over\ntwo orders of magnitude in large circuits. NN-PARS also provides high accuracy\nlevels in signal waveform calculations, with less than 2 % error compared to\nHSPICE.\n