2020/07/26 by Jhang-Yan Ciou, Sourav De, Ciou, Jhang-Yan +8
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Applied Physics (physics.app-ph) #FOS: Physical sciences #Ferroelectric and Negative Capacitance Devices #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.2007.13168
openalex publication_date 2020/07/26 · openalex created_date 2021/01/18 · openalex updated_date 2026/07/28
This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.