2013/09/22 by Sparsh Mittal, Mittal, Sparsh
Computer Science · Engineering · #Cloud Computing and Resource Management #FOS: Computer and information sciences #Green IT and Sustainability #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Parallel Computing and Optimization Techniques #Radiation Effects in Electronics
paper · pdf · doi:10.48550/arxiv.1309.5647
openalex publication_date 2013/09/22 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
There has been a significant increase in leakage energy dissipation of CMOS\ncircuits with each technology generation. Further, due to their large size,\nlast level caches (LLCs) spend a large fraction of their energy in the form of\nleakage energy and hence, addressing this has become extremely important to\nmeet the challenges of chip power budget. For addressing this, several\ntechniques have been proposed. However, most of these techniques require\noffline profiling and hence cannot be used for real-life systems which usually\nrun multitasking programs, with possible pre-emptions. In this paper, we\npropose a dynamic profiling based technique for saving cache leakage energy in\nmultitasking systems. Our technique uses a small coloring-based profiling\ncache, to estimate performance and energy consumption of multiple cache\nconfigurations and then selects the best (least-energy) configuration among\nthem. Our technique uses non-intrusive profiling and saves energy despite\nintra-task and inter-task variations; thus, it is suitable for multitasking\nsystems. Simulations performed using workloads from SPEC2006 suite show the\nsuperiority of our technique over an existing cache energy saving technique.\nWith a 2MB baseline cache, the average saving in memory sub-system energy is\n22.8%.\n