2013/10/31 by Sparsh Mittal, Mittal, Sparsh
Engineering · Computer Science · #Advanced Memory and Neural Computing #Ferroelectric and Negative Capacitance Devices #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.1311.0041
Due to increasing cache sizes and large leakage consumption of SRAM device,\nconventional SRAM caches contribute significantly to the processor power\nconsumption. Recently researchers have used non-volatile memory devices to\ndesign caches, since they provide high density, comparable read latency and low\nleakage power dissipation. However, their high write latency may increase the\nexecution time and hence, leakage energy consumption. Also, since their write\nendurance is small, a conventional energy saving technique may further\naggravate the problem of write-variations, thus reducing their lifetime. In\nthis paper, we present a cache energy saving technique for non-volatile caches,\nwhich also attempts to improve their lifetime by making writes equally\ndistributed to the cache. Our technique uses dynamic cache reconfiguration to\nadjust the cache size to meet program requirement and turns off the remaining\ncache to save energy. Microarchitectural simulations performed using an x86-64\nsimulator, SPEC2006 benchmarks and a resistive-RAM LLC (last level cache) show\nthat over an 8MB baseline cache, our technique saves 17.55% memory subsystem\n(last level cache + main memory) energy and improves the lifetime by 1.33X.\nOver the same resistive-RAM baseline, an SRAM of similar area with no cache\nreconfiguration leads to an energy loss of 186.13%.\n