Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM

2005/01/01 by Daniel Mossé, Mossé, Daniel, Nevine AbouGhazaleh +5
Computer Science · Engineering · #Advanced Data Storage Technologies #Low-power high-performance VLSI design #Memory power management #Parallel Computing and Optimization Techniques #cached DRAM

paper · doi:10.4230/dagsemproc.05141.5

openalex publication_date 2005/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a new memory organization, called em Power-Aware Cached-DRAM (PA-CDRAM), that integrates a moderately sized cache directly into a memory device. We use this cache to turn a memory bank off immediately after a memory access to reduce energy consumption. While other work has used CDRAM to improve memory performance, we modify CDRAM to reduce energy consumption. In this paper, we describe our memory organization and describe the challenges for achieving low energy consumption and how to address them. We evaluate the approach using a cycle accurate processor and memory simulator. Our results show that PA-CDRAM achieves an average 28% improvement in the energy-delay product when compared to a time-out power management technique.

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