2019/11/12 by Mehrzad Nejat, Madhavan Manivannan, Nejat, Mehrzad +5 · 1 citation
Computer Science · #Caching and Content Delivery #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.1911.05114
openalex publication_date 2019/11/12 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
An effective way to improve energy efficiency is to throttle hardware\nresources to meet a certain performance target, specified as a QoS constraint,\nassociated with all applications running on a multicore system.\n Prior art has proposed resource management (RM) frameworks in which the share\nof the last-level cache (LLC) assigned to each processor and the\nvoltage-frequency (VF) setting for each processor is managed in a coordinated\nfashion to reduce energy. A drawback of such a scheme is that, while one core\ngives up LLC resources for another core, the performance drop must be\ncompensated by a higher VF setting which leads to a quadratic increase in\nenergy consumption. By allowing each core to be adapted to exploit instruction\nand memory-level parallelism (ILP/MLP), substantially higher energy savings are\nenabled.\n This paper proposes a coordinated RM for LLC partitioning, processor\nadaptation, and per-core VF scaling. A first contribution is a systematic study\nof the resource trade-offs enabled when trading between the three classes of\nresources in a coordinated fashion. A second contribution is a new RM framework\nthat utilizes these trade-offs to save more energy. Finally, a challenge to\naccurately model the impact of resource throttling on performance is to predict\nthe amount of MLP with high accuracy. To this end, the paper contributes with a\nmechanism that estimates the effect of MLP over different processor\nconfigurations and LLC allocations. Overall, we show that up to 18% of energy,\nand on average 10%, can be saved using the proposed scheme.\n